The present invention relates generally to integrated circuit testing techniques and, more particularly, to a dense register array and method for enabling scan out observation of both L1 and L2 latches.
As the packing density of integrated circuit devices has increased greatly in recent years, various schemes have been devised for providing increased testability of the devices. For example, if it is desired to operate an integrated circuit from a known initial state, it is often necessary to be able to input states into the various latches and flip-flops from an external data pin. It is further useful to be able to test the integrated circuit by shifting a test vector comprised of a sequence of bits through a chain of latches and/or flip-flops to ensure the integrated circuit is functioning properly. To this end, the various storage elements have been designed so as to have two modes of operation. In a first mode of operation, the storage elements are set in a “functional” mode such that the integrated circuit performs its normal operational tasks. In a second or “shift” mode, data is shifted through the storage elements and out through an output pin of the integrated circuit for diagnostic analysis.
One particularly effective testing scheme employs a level sensitive scan design (LSSD) in which separate system and scan clocks are used to distinguish between normal and test modes. In particular, latches are used in pairs, wherein each has a normal data input, data output and clock for system operation. In the functional mode, the storage element is a level sensitive latch that is controlled by the system clock. In the shift mode, the two latches form a master/slave pair with one scan input, one scan output, and non-overlapping scan clocks A and B that are held low during system operation but cause the scan data to be latched when pulsed high during scan.
Register arrays that comprise a single latch per memory data bit form a dense memory function. The testing of such register arrays using existing scan techniques (i.e., 2 latches at a time performing 1 scan shift bit) allows the register arrays to fill a window in a memory size versus chip area menu. While smaller memories may be realized with flip-flops (2 latches per memory data bit), larger memories are typically realized by dense arrays of non-scannable memory cells where the memory is tested using Array Built in Self Test (ABIST).